Functional Description
Page 15
Figure 4 shows an FPP configuration schematic with the external flash interface in
use.
Figure 4. FPP Configuration with External Flash Interface (1)
EPC Device
V
PLD or Processor
V
CC
CC
Stratix Series
or
APEX II Device
WE#C
WE#
RP#
WE#F
RP#F
RP#C
DCLK
DATA[7..0]
OE
nCS
nINIT_CONF
DCLK
n
A[20..0]
RY/BY#
CE#
A[20..0] (2)
RY/BY# (5)
CE#
DATA[7..0]
nSTATUS
CONF_DONE
nCONFIG
MSEL
nCEO
OE#
OE#
N.C.
DQ[15..0]
DQ[15..0]
nCE
V
CC
V
(6)
CC
WP#
BYTE# (3)
VCCW
GND
TM1
PORSEL
(4)
(4)
PGM[2..0]
TMO
EXCLK
(4)
GND
C-A0 (3)
C-A1 (3)
C-A15 (3)
C-A16 (3)
A0-F
A1-F
A15-F
A16-F
Notes to Figure 4:
(1) For external flash interface support in the EPC8 device, contact Altera Applications 24/7 Technical Support.
(2) Pin A20in EPC16 devices, pins A20and A19in EPC8 devices, and pins A20 A19, and A18in EPC4 devices should be left floating. These pins
should not be connected to any signal as they are NC pins.
(3) In the 100-pin PQFP package, you must externally connect the following pins: C-A0to F-A0
F-A16, andBYTE#to VCC. Additionally, you must make the following pin connections in both 100-pin PQFP and 88-pin UFBGA packages: C-RP#
to F-RP# C-WE#to F-WE# TM1to VCC, TM0to GND, and WP#to VCC
(4) For PORSEL PGM[], and EXCLKpin connections, refer to Table 10 on page 24.
,
,
C-A1to F-A1, C-A15to F-A15, C-A16to
,
,
.
,
(5) RY/BY#pin is only available for Sharp flash-based EPC8 and EPC16 devices.
(6) To protect Intel Flash based EPC devices content, isolate the VCCW supply from VCC. For more information, refer to “Intel Flash-Based EPC Device
Protection” on page 16.
January 2012 Altera Corporation
Enhanced Configuration (EPC) Devices Datasheet
ALTERA [ ALTERA CORPORATION ]
