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EPC16QI100N 参数 Datasheet PDF下载

EPC16QI100N图片预览
型号: EPC16QI100N
PDF下载: 下载PDF文件 查看货源
内容描述: 该数据表描述了增强型配置( EPC )设备 [This datasheet describes enhanced configuration (EPC) devices]
分类和应用: 存储内存集成电路LTEPC可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 36 页 / 621 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Page 10  
Functional Description  
Fast Passive Parallel Configuration  
Stratix series and APEX II devices can be configured using the EPC device in the FPP  
configuration mode. In this mode, the EPC device sends a byte of data on the  
DATA[7..0]pins, which connect to the DATA[7..0]input pins of the FPGA, per DCLK  
cycle. Stratix series and APEX II FPGAs receive byte-wide configuration data per DCLK  
cycle. Figure 2 shows the EPC device in FPP configuration mode. In this figure, the  
external flash interface is not used and hence most flash pins are left unconnected  
(with the few noted exceptions).  
f For more information about configuration interface connections including the pull-up  
resistor values, supply voltages, and MSELpin settings, refer to the configuration  
chapter in the appropriate device handbook.  
Figure 2. FPP Configuration  
EPC Device  
V
CC  
V
(1)  
CC  
(1)  
Stratix Series  
or  
APEX II Device  
WE#C  
RP#C  
DCLK  
WE#F  
RP#F  
(3)  
(3)  
n
DCLK  
(6)  
MSEL  
A[20..0]  
RY/BY#  
CE#  
N.C.  
N.C.  
N.C.  
N.C.  
N.C.  
DATA[7..0]  
nSTATUS  
CONF_DONE  
nCONFIG  
DATA[7..0]  
(3)  
OE  
(3)  
nCS  
nINIT_CONF (2)  
OE#  
V
(1)  
CC  
DQ[15..0]  
nCE  
N.C.  
nCEO  
V
(7)  
WP#  
CC  
BYTE# (5)  
TM1  
VCCW  
GND  
(4)  
PORSEL  
(4)  
PGM[2..0]  
(4)  
TMO  
EXCLK  
GND  
C-A0 (5)  
C-A1 (5)  
C-A15 (5)  
C-A16 (5)  
A0-F  
A1-F  
A15-F  
A16-F  
Notes to Figure 2:  
(1) The VCC should be connected to the same supply voltage as the EPC device.  
(2) The nINIT CONFpin is available on EPC devices and has an internal pull-up resistor that is always active. This means an external pull-up  
resistor is not required on the nINIT CONFor nCONFIGsignal. The nINIT CONFpin does not need to be connected if its functionality is not  
used. If nINIT CONFis not used, nCONFIGmust be pulled to VCC either directly or through a resistor.  
_
_
_
_
(3) The EPC devices’ OEand nCSpins have internal programmable pull-up resistors. If internal pull-up resistors are used, external pull-up resistors  
should not be used on these pins. The internal pull-up resistors are used by default in the QuartusII software. To turn off the internal pull-up  
resistors, check the Disable nCS and OE pull-ups on configuration device option when generating programming files.  
(4) For PORSEL  
(5) In the 100-pin PQFP package, you must externally connect the following pins: C-A0to F-A0  
F-A16, andBYTE#to VCC. Additionally, you must make the following pin connections in both 100-pin PQFP and 88-pin UFBGA packages: C-RP#  
to F-RP# C-WE#to F-WE# TM1to VCC, TM0to GND, and WP#to VCC  
, PGM[], and EXCLKpin connections, refer to Table 10 on page 24.  
,
C-A1to F-A1, C-A15to F-A15, C-A16to  
,
,
.
(6) Connect the FPGA MSEL[]input pins to select the FPP configuration mode. For more information, refer to the configuration chapter in the  
appropriate device handbook.  
(7) To protect Intel Flash-based EPC devices content, isolate the VCCW supply from VCC. For more information, refer to “Intel Flash-Based EPC Device  
Protection” on page 16.  
Enhanced Configuration (EPC) Devices Datasheet  
January 2012 Altera Corporation