欢迎访问ic37.com |
会员登录 免费注册
发布采购

EPC16QI100N 参数 Datasheet PDF下载

EPC16QI100N图片预览
型号: EPC16QI100N
PDF下载: 下载PDF文件 查看货源
内容描述: 该数据表描述了增强型配置( EPC )设备 [This datasheet describes enhanced configuration (EPC) devices]
分类和应用: 存储内存集成电路LTEPC可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 36 页 / 621 K
品牌: ALTERA [ ALTERA CORPORATION ]
 浏览型号EPC16QI100N的Datasheet PDF文件第12页浏览型号EPC16QI100N的Datasheet PDF文件第13页浏览型号EPC16QI100N的Datasheet PDF文件第14页浏览型号EPC16QI100N的Datasheet PDF文件第15页浏览型号EPC16QI100N的Datasheet PDF文件第17页浏览型号EPC16QI100N的Datasheet PDF文件第18页浏览型号EPC16QI100N的Datasheet PDF文件第19页浏览型号EPC16QI100N的Datasheet PDF文件第20页  
Page 16  
Functional Description  
Intel Flash-Based EPC Device Protection  
In the absence of the lock bit protection feature in the EPC4, EPC8, and EPC16 devices  
with Intel flash, Altera recommends four methods to protect the Intel Flash content in  
EPC4, EPC8, and EPC16 devices. Any method alone is sufficient to protect the flash.  
The methods are listed here in the order of descending protection level:  
1. Using an RP#of less than 0.3 V on power-up and power-down for a minimum of  
100 ns to a maximum 25 ms disables all control pins, making it impossible for a  
write to occur.  
2. Using VPP < VPPLK, where the maximum value of VPPLK is 1 V, disables writes.  
VPP < VPPLK means programming or writes cannot occur. VPP is a programming  
supply voltage input pin on the Intel flash. VPP is equivalent to the VCCWpin on  
EPC devices.  
3. Using a high CE#disables the chip. The requirement for a write is a low CE#and  
low WE#.A high CE#by itself prevents writes from occurring.  
4. Using a high WE#prevent writes because a write only occurs when the WE#is low.  
Performing all four methods simultaneously is the safest protection for the flash  
content.  
The following lists the ideal power-up sequence:  
1. Power up VCC  
2. Maintain VPP < VPPLK until VCC is fully powered up.  
3. Power up VPP  
.
.
4. Drive RP#low during the entire power-up process. RP#must be released high  
within 25 ms after VPP is powered up.  
1
1
CE#and WE#must be high for the entire power-up sequence.  
The following lists the ideal power-down sequence:  
1. Drive RP#low for 100 ns before power-down.  
2. Power down VPP < VPPLK  
3. Power down VCC  
.
.
4. Drive RP#low during the entire power-down process.  
CE#and WE#must be high for the entire power-down sequence.  
The RP#pin is not internally connected to the controller. Therefore, an external  
loop-back connection between C-RP#and F-RP#must be made on the board even  
when you are not using the external device to the RP#pin with the loop-back  
connection. Always tri-state RP#when the flash is not in use.  
Enhanced Configuration (EPC) Devices Datasheet  
January 2012 Altera Corporation  
 复制成功!