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Functional Description
The EPC device controller chip accesses flash memory during:
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FPGA configuration—reading configuration data from flash
JTAG-based flash programming—storing configuration data in flash
At POR—reading option bits from flash
During these operations, the external FPGA or processor must tri-state its interface to
the flash memory. After configuration and programming, the EPC device’s controller
tri-states the internal interface and goes into an idle mode. To interrupt a
configuration cycle in order to access the flash using the external flash interface, the
external device can hold the FPGA’s nCONFIGinput low. This keeps the configuration
device in reset by holding the nSTATUS-OEline low, allowing external flash access.
f For more information about the software support for the external flash interface
feature, refer to the Altera Enhanced Configuration Devices.
Enhanced Configuration (EPC) Devices Datasheet
January 2012 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
