Functional Description
Page 9
Finally, the configuration controller also manages errors during configuration. A
CONF DONEerror occurs when the FPGA does not de-assert its CONF DONEsignal within
64 DCLKcycles after the last bit of configuration data is transmitted. When a CONF DONE
_
_
_
error is detected, the controller pulses the OEline low, which pulls the nSTATUSsignal
low and triggers another configuration cycle.
A cyclic redundancy check (CRC) error occurs when the FPGA detects corruption in
the configuration data. This corruption could be a result of noise coupling on the
board such as poor signal integrity on the configuration signals. When this error is
signaled by the FPGA (by driving the nSTATUSsignal low), the controller stops
configuration. If the Auto-Restart Configuration After Error option is enabled in the
FPGA, it releases its nSTATUSsignal after a reset time-out period and the controller
attempts to reconfigure the FPGA.
After the FPGA configuration process is complete, the controller drives the DCLKpin
low and the DATA[]pins high. Additionally, the controller tri-states its internal
interface to the flash memory, enables the weak internal pull-ups on the flash address
and control lines, and enables bus-keep circuits on flash data lines.
The following sections describe the different configuration schemes supported by the
EPC device—FPP, PS, and concurrent configuration schemes.
f For more information, refer to the configuration chapter in the appropriate device
handbook.
Configuration Signals
Table 4 lists the configuration signal connections between the EPC device and Altera
FPGAs.
Table 4. Configuration Signals
EPC Device Pin
Altera FPGA Pin
Description
Configuration data transmitted from the EPC device to the
DATA[]
DATA[]
FPGA, which is latched on the rising edge of DCLK
.
EPC device generated clock used by the FPGA to latch
configuration data provided on the DATA[]pins.
DCLK
DCLK
Open-drain output from the EPC device that is used to
start FPGA reconfiguration using the initiate configuration
(
INIT
needed if the INIT
If INIT CONFis not connected to nCONFIG, nCONFIG
_
CONF) JTAG instruction. This connection is not
nINIT_CONF,
which
nCONFIG
_
CONFJTAG instruction is not needed.
n
_
must be tied to VCC either directly or through a pull-up
resistor.
Open-drain bidirectional configuration status signal,
which is driven low by either the EPC device or FPGA
during POR and to signal an error during configuration.
Low pulse on OEresets the EPC device controller.
OE
nSTATUS
nCS
CONF_DONE
Configuration done output signal driven by the FPGA.
January 2012 Altera Corporation
Enhanced Configuration (EPC) Devices Datasheet
ALTERA [ ALTERA CORPORATION ]
