Chapter 1: Cyclone III Device Data Sheet
1–27
I/O Timing
I/O Timing
You can use the following methods to determine the I/O timing:
■
the Excel-based I/O Timing.
the Quartus II timing analyzer.
■
The Excel-based I/O Timing provides pin timing performance for each device density
and speed grade. The data is typically used prior to designing the FPGA to get a
timing budget estimation as part of the link timing analysis. The Quartus II timing
analyzer provides a more accurate and precise I/O timing data based on the specifics
of the design after place-and-route is complete.
f
The Excel-based I/O Timing spreadsheet is downloadable from Cyclone III Devices
Literature website.
Glossary
Table 1–39 lists the glossary for this chapter.
Table 1–39. Glossary (Part 1 of 5)
Letter
Term
—
Definitions
A
B
C
D
E
—
—
—
—
—
—
—
—
—
F
fHSCLK
HIGH-SPEED I/O Block: High-speed receiver/transmitter input and output clock frequency.
Input pin directly to Global Clock network.
GCLK
G
H
GCLK PLL
HSIODR
Input pin to Global Clock network through PLL.
HIGH-SPEED I/O Block: Maximum/minimum LVDS data transfer rate (HSIODR = 1/TUI).
VIH
Input Waveforms
for the SSTL
Differential I/O
Standard
I
VSWING
VREF
VIL
© January 2010 Altera Corporation
Cyclone III Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
