1–16
Chapter 1: Cyclone III Device Data Sheet
Switching Characteristics
Table 1–20. Cyclone III Devices PLL Specifications (Note 1) (Part 2 of 2)
Symbol
Parameter
Min
—
—
—
45
Typ
—
—
—
50
—
Max
472.5
450
402.5
55
Unit
MHz
MHz
MHz
%
PLL output frequency (–6 speed grade)
PLL output frequency (–7 speed grade)
PLL output frequency (–8 speed grade)
Duty cycle for external clock output (when set to 50%)
Time required to lock from end of device configuration
fOUT (to global clock)
tOUTDUTY
tLOCK
—
1
ms
Time required to lock dynamically (after switchover,
reconfiguring any non-post-scale counters/delays or
areset is deasserted)
tDLOCK
—
—
1
ms
Dedicated clock output period jitter
FOUT ≥ 100 MHz
—
—
—
—
—
—
—
—
—
—
—
—
—
—
300
30
ps
mUI
ps
tOUTJITTER_PERIOD_DEDCLK (5)
FOUT < 100 MHz
Dedicated clock output cycle-to-cycle jitter
FOUT ≥ 100 MHz
300
30
tOUTJITTER_CCJ_DEDCLK (5)
tOUTJITTER_PERIOD_IO (5)
tOUTJITTER_CCJ_IO (5)
FOUT < 100 MHz
mUI
ps
Regular I/O period jitter
FOUT ≥ 100 MHz
650
75
FOUT < 100 MHz
mUI
ps
Regular I/O cycle-to-cycle jitter
FOUT ≥ 100 MHz
650
F
OUT < 100 MHz
—
—
10
—
—
—
75
50
—
mUI
ps
tPLL_PSERR
tARESET
Accuracy of PLL phase shift
Minimum pulse width on areset signal.
ns
SCANCLK
cycles
tCONFIGPLL
Time required to reconfigure scan chains for PLLs
—
—
3.5 (6)
—
fSCANCLK
scanclk frequency
—
100
MHz
Notes to Table 1–20:
(1) VCCD_PLL should always be connected to VCCINT through decoupling capacitor and ferrite bead.
(2) This parameter is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O standard.
(3) The VCO frequency reported by the Quartus II software in the PLL summary section of the compilation report takes into consideration the VCO post-scale
counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the fVCO specification.
(4) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source, which is less than 200 ps.
(5) Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies to the intrinsic
jitter of the PLL, when an input jitter of 30 ps is applied.
(6) With 100 MHz scanclk frequency.
Cyclone III Device Handbook, Volume 2
© January 2010 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
