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EP2C8T144I8N 参数 Datasheet PDF下载

EP2C8T144I8N图片预览
型号: EP2C8T144I8N
PDF下载: 下载PDF文件 查看货源
内容描述: Cyclone II器件手册,卷1 [Cyclone II Device Handbook, Volume 1]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 470 页 / 5765 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Configuring Cyclone II Devices  
Table 13–12 describes the optional configuration pins. If these optional  
configuration pins are not enabled in the Quartus II software, they are  
available as general-purpose user I/O pins. Therefore during  
configuration, these pins function as user I/O pins and are tri-stated with  
weak pull-up resistors.  
Table 13–12. Optional Configuration Pins  
Pin Name User Mode Pin Type  
CLKUSR  
Description  
N/A if option is Input  
on. I/O if option  
is off.  
This is an optional user-supplied clock input that  
synchronizes the initialization of one or more devices. This  
pin is enabled by turning on the Enable user-supplied  
start-up clock (CLKUSR) option in the Quartus II software  
N/A if option is Output open-  
on. I/O if option drain  
is off.  
This is a status pin that can be used to indicate when the  
device has initialized and is in user mode. When nCONFIG  
is low and during the beginning of configuration, the  
INIT_DONEpin is tri-stated and pulled high due to an  
external 10-kΩ pull-up resistor. Once the option bit to  
enable INIT_DONEis programmed into the device (during  
the first frame of configuration data), the INIT_DONEpin  
goes low. When initialization is complete, the INIT_DONE  
pin is released and pulled high and the FPGA enters user  
mode. Thus, the monitoring circuitry must be able to detect  
a low-to-high transition. This pin is enabled by turning on  
the Enable INIT_DONE output option in the Quartus II  
software.  
INIT_DONE  
N/A if option is Input  
on. I/O if option  
is off.  
Optional pin that allows the user to override all tri-states on  
the device. When this pin is driven low, all I/O pins are tri-  
stated. When this pin is driven high, all I/O pins behave as  
programmed. This pin is enabled by turning on the Enable  
device-wide output enable (DEV_OE) option in the  
Quartus II software.  
DEV_OE  
N/A if option is Input  
on. I/O if option  
is off.  
Optional pin that allows you to override all clears on all  
device registers. When this pin is driven low, all registers  
are cleared. When this pin is driven high, all registers  
behave as programmed. This pin is enabled by turning on  
the Enable device-wide reset (DEV_CLRn) option in the  
Quartus II software.  
DEV_CLRn  
Altera Corporation  
February 2007  
13–69  
Cyclone II Device Handbook, Volume 1  
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