Device Configuration Pins
Table 13–11. Dedicated Configuration Pins on the Cyclone II Device (Part 5 of 5)
User Configuration
Pin Name
DCLK
Pin Type
Description
Mode
Scheme
N/A
PS,
AS
Input (PS)
Output (AS)
In PS configuration, DCLKis the clock input used to
clock data from an external source into the target
device. Data is latched into the Cyclone II device on
the rising edge of DCLK.
In AS mode, DCLKis an output from the Cyclone II
device that provides timing for the configuration
interface. In AS mode, DCLKhas an internal pull-up
that is always active.
After configuration, this pin is tri-stated. If you are
using a configuration device, it drives DCLKlow after
configuration is complete. If your design uses a
control host, drive DCLKeither high or low. Toggling
this pin after configuration does not affect the
configured device.
The input buffer on this pin supports hysteresis using
Schmitt trigger circuitry.
N/A
All
Input
This is the data input pin. In serial configuration
modes, bit-wide configuration data is presented to the
target device on the DATA0pin.
DATA0
In AS mode, DATA0has an internal pull-up resistor
that is always active.
After configuration, EPC1 and EPC1441 devices
tri-state this pin, while enhanced configuration and
EPC2 devices drive this pin high.
The input buffer on this pin supports hysteresis using
Schmitt trigger circuitry.
13–68
Altera Corporation
February 2007
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
