14. IEEE 1149.1 (JTAG)
Boundary-Scan Testing for
Cyclone II Devices
CII51014-2.1
As printed circuit boards (PCBs) become more complex, the need for
thorough testing becomes increasingly important. Advances in surface-
mount packaging and PCB manufacturing have resulted in smaller
boards, making traditional test methods (e.g., external test probes and
“bed-of-nails” test fixtures) harder to implement. As a result, cost savings
from PCB space reductions are sometimes offset by cost increases in
traditional testing methods.
Introduction
In the 1980s, the Joint Test Action Group (JTAG) developed a specification
for boundary-scan testing that was later standardized as the
IEEE Std. 1149.1 specification. This boundary-scan test (BST) architecture
offers the capability to efficiently test components on PCBs with tight lead
spacing.
This BST architecture tests pin connections without using physical test
probes and captures functional data while a device is operating normally.
Boundary-scan cells in a device force signals onto pins or capture data
from pin or logic array signals. Forced test data is serially shifted into the
boundary-scan cells. Captured data is serially shifted out and externally
compared with expected results. Figure 14–1 shows the concept of
boundary-scan testing.
Figure 14–1. IEEE Std. 1149.1 Boundary-Scan Testing
Boundary-Scan Cell
Serial
Data In
Serial
Data Out
IC Pin Signal
Core
Logic
Core
Logic
Tested
Connection
JTAG Device 1
JTAG Device 2
Altera Corporation
February 2007
14–1
ALTERA [ ALTERA CORPORATION ]
