欢迎访问ic37.com |
会员登录 免费注册
发布采购

EP2C8T144I8N 参数 Datasheet PDF下载

EP2C8T144I8N图片预览
型号: EP2C8T144I8N
PDF下载: 下载PDF文件 查看货源
内容描述: Cyclone II器件手册,卷1 [Cyclone II Device Handbook, Volume 1]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 470 页 / 5765 K
品牌: ALTERA [ ALTERA CORPORATION ]
 浏览型号EP2C8T144I8N的Datasheet PDF文件第420页浏览型号EP2C8T144I8N的Datasheet PDF文件第421页浏览型号EP2C8T144I8N的Datasheet PDF文件第422页浏览型号EP2C8T144I8N的Datasheet PDF文件第423页浏览型号EP2C8T144I8N的Datasheet PDF文件第425页浏览型号EP2C8T144I8N的Datasheet PDF文件第426页浏览型号EP2C8T144I8N的Datasheet PDF文件第427页浏览型号EP2C8T144I8N的Datasheet PDF文件第428页  
Conclusion  
Table 13–13 describes the dedicated JTAG pins. JTAG pins must be kept  
stable before and during configuration to prevent accidental loading of  
JTAG instructions. The TCKpin has a weak internal pull-down resistor  
and the TDIand TMSJTAG input pins have weak internal pull-up  
resistors.  
Table 13–13. Dedicated JTAG Pins  
Pin Name User Mode Pin Type  
TDI  
Description  
N/A  
Input  
Serial input pin for instructions as well as test and programming  
data. Data is shifted in on the rising edge of TCK.  
If the JTAG interface is not required on the board, the JTAG  
circuitry can be disabled by connecting this pin to VCC  
.
The input buffer on this pin supports hysteresis using Schmitt  
trigger circuitry.  
N/A  
N/A  
Output  
Serial data output pin for instructions as well as test and  
programming data. Data is shifted out on the falling edge of  
TCK. The pin is tri-stated if data is not being shifted out of the  
device.  
TDO  
TMS  
If the JTAG interface is not required on the board, the JTAG  
circuitry can be disabled by leaving this pin unconnected.  
Input  
Input pin that provides the control signal to determine the  
transitions of the TAP controller state machine. Transitions  
within the state machine occur on the rising edge of TCK.  
Therefore, TMS must be set up before the rising edge of TCK.  
TMS is evaluated on the rising edge of TCK.  
If the JTAG interface is not required on the board, the JTAG  
circuitry can be disabled by connecting this pin to VCC  
.
The input buffer on this pin supports hysteresis using Schmitt  
trigger circuitry.  
N/A  
Input  
The clock input to the BST circuitry. Some operations occur at  
the rising edge, while others occur at the falling edge.  
TCK  
If the JTAG interface is not required on the board, the JTAG  
circuitry can be disabled by connecting this pin to GND.  
The input buffer on this pin supports hysteresis using Schmitt  
trigger circuitry.  
Cyclone II devices can be configured in AS, PS or JTAG configuration  
schemes to fit your system's need. The AS configuration scheme  
supported by Cyclone II devices can now operate at a higher DCLK  
Conclusion  
13–70  
Altera Corporation  
Cyclone II Device Handbook, Volume 1  
February 2007  
 复制成功!