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EP2C8T144I8N 参数 Datasheet PDF下载

EP2C8T144I8N图片预览
型号: EP2C8T144I8N
PDF下载: 下载PDF文件 查看货源
内容描述: Cyclone II器件手册,卷1 [Cyclone II Device Handbook, Volume 1]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 470 页 / 5765 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Device Configuration Pins  
Table 13–11. Dedicated Configuration Pins on the Cyclone II Device (Part 3 of 5)  
User Configuration  
Pin Name  
Pin Type  
Description  
Mode  
Scheme  
N/A  
All  
Bidirectional  
open-drain  
This pin is a status output and input.  
CONF_DONE  
The target Cyclone II device drives the CONF_DONE  
pin low before and during configuration. Once the  
Cyclone II device receives all the configuration data  
without error and the initialization cycle starts, it  
releases CONF_DONE. Driving CONF_DONElow  
during user mode does not affect the configured  
device. Do not drive CONF_DONElow before the  
device enters user mode.  
After the Cyclone II device receives all the data, the  
CONF_DONEpin transitions high, and the device  
initializes and enters user mode. The CONF_DONE  
pin must have an external 10-kΩ pull-up resistor in  
order for the device to initialize.  
Driving CONF_DONElow after configuration and  
initialization does not affect the configured device.  
The enhanced configuration devices’ and EPC2  
devices’ OEand nCSpins are connected to the  
Cyclone II device’s nSTATUSand CONF_DONEpins,  
respectively, and have optional internal  
programmable pull-up resistors. If internal pull-up  
resistors on the enhanced configuration device are  
used, external 10-kΩ pull-up resistors should not be  
used on these pins. When using EPC2 devices, you  
should only use external 10-kΩ pull-up resistors.  
The input buffer on this pin supports hysteresis using  
Schmitt trigger circuitry.  
N/A  
All  
Input  
nCE  
This pin is an active-low chip enable. The nCEpin  
activates the device with a low signal to allow  
configuration. The nCEpin must be held low during  
configuration, initialization, and user mode. In single  
device configuration, it should be tied low. In multiple  
device configuration, nCEof the first device is tied low  
while its nCEOpin is connected to nCEof the next  
device in the chain.  
The nCEpin must also be held low for successful  
JTAG programming of the FPGA.  
The input buffer on this pin supports hysteresis using  
Schmitt trigger circuitry.  
13–66  
Altera Corporation  
February 2007  
Cyclone II Device Handbook, Volume 1  
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