DC & Switching Characteristics
Table 6–91 describes the Stratix GX device fast PLL specifications.
Table 6–91. Fast PLL Specifications for -5 & -6 Speed Grade Devices
Symbol
Parameter
Min
Max
Unit
fIN
CLKINfrequency (for m = 1) (1)
CLKINfrequency (for m = 2 to 19)
300
717
MHz
MHz
300/
1,000/m
m
CLKINfrequency (for m = 20 to 32)
10
1,000/m
MHz
MHz
fOUT
Output frequency for internal global or
9.4
420
regional clock (2)
fOUT_EXT
fVCO
Output frequency for external clock
VCO operating frequency
9.375
300
40
717
1,000
60
MHz
MHz
%
tINDUTY
tINJITTER
tDUTY
CLKINduty cycle
Period jitter for CLKINpin
200
55
ps
Duty cycle for DFFIO1× CLKOUTpin (3)
Period jitter for DIFFIO clock out (3)
45
%
tJITTER
80
ps
Period jitter for internal global or
regional clock
100 ps for >200-MHz outclk
20 mUI for <200-MHz outclk
ps or
mUI
tLOCK
m
Time required for PLL to acquire lock
10
1
100
32
μs
Multiplication factors for m counter (3)
Integer
Integer
l0, l1, g0
Multiplication factors for l0, l1, and g0
counter (4), (5)
1
32
tARESET
10
ns
Minimum pulse width on areset
signal
Table 6–92. Fast PLL Specifications for -7 & -8 Speed Grades (Part 1 of 2)
Symbol
Parameter
Min
Max
Unit
fIN
CLKINfrequency (for m = 1) (1),
CLKINfrequency (for m = 2 to 19)
300
640
MHz
MHz
300/
700/m
m
CLKINfrequency (for m = 20 to 32)
10
700/m
MHz
MHz
fOUT
Output frequency for internal global or 9.375
420
regional clock (2)
fOUT_EXT
fVCO
tINDUTY
tINJITTER
Output frequency for external clock
VCO operating frequency
CLKINduty cycle
9.4
300
40
500
700
60
MHz
MHz
%
Period jitter for CLKINpin
200
ps
Altera Corporation
June 2006
6–67
Stratix GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
