Stratix GX Architecture
Table 4–23 shows the number of DQ and DQS buses that are supported
per device.
Table 4–23. DQS & DQ Bus Mode Support
Device Package
Note (1)
Number of ×8
Groups
Number of ×16
Groups
Number of ×32
Groups
EP1SGX10 672-pin FineLine BGA
EP1SGX25 672-pin FineLine BGA
1,020-pin FineLine BGA
12 (2)
16 (3)
20
0
8
8
8
0
4
4
4
EP1SGX40 1,020-pin FineLine BGA
20
Notes to Table 4–23:
(1) See the Selectable I/O Standards in Stratix & Stratix GX Devices chapter of the Stratix GX Device Handbook,
Volume 2 for VREF guidelines.
(2) These packages have six groups in I/O banks 3 and 4 and six groups in I/O banks 7 and 8.
(3) These packages have eight groups in I/O banks 3 and 4 and eight groups in I/O banks 7 and 8.
A compensated delay element on each DQS pin automatically aligns
input DQS synchronization signals with the data window of their
corresponding DQ data signals. The DQS signals drive a local DQS bus in
the top and bottom I/O banks. This DQS bus is an additional resource to
the I/O clocks and clocks DQ input registers with the DQS signal.
Two separate single phase-shifting reference circuits are located on the
top and bottom of the Stratix GX device. Each circuit is driven by a system
reference clock through the CLKpins that is the same frequency as the
DQS signal. Clock pins CLK[15..12]pfeed the phase-shift circuitry on
the top of the device and clock pins CLK[7..4]pfeed the phase-shift
circuitry on the bottom of the device. The phase-shifting reference circuit
on the top of the device controls the compensated delay elements for all
10 DQS pins located at the top of the device. The phase-shifting reference
circuit on the bottom of the device controls the compensated delay
elements for all 10 DQS pins located on the bottom of the device. All
10 delay elements (DQS signals) on either the top or bottom of the device
shift by the same degree amount. For example, all 10 DQS pins on the top
of the device can be shifted by 90° and all 10 DQS pins on the bottom of
the device can be shifted by 72°. The reference circuits require a maximum
of 256 system reference clock cycles to set the correct phase on the DQS
delay elements. Figure 4–68 illustrates the phase-shift reference circuit
control of each DQS delay shift on the top of the device. This same circuit
is duplicated on the bottom of the device.
Altera Corporation
February 2005
4–109
Stratix GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
