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EP1SGX40GF1020I6 参数 Datasheet PDF下载

EP1SGX40GF1020I6图片预览
型号: EP1SGX40GF1020I6
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 4697 CLBs, 41250-Cell, CMOS, PBGA1020, 33 X 33 MM, 1 MM PITCH, FBGA-1020]
分类和应用: 可编程逻辑
文件页数/大小: 272 页 / 1348 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Stratix GX Architecture  
Figure 4–65. Input Timing Diagram in DDR Mode  
Data at  
input pin  
A0 B1 A1 B2 A2 B3 A3 B4  
CLK  
A'  
A1  
B1  
A2  
B2  
A3  
B3  
Input To  
Logic Array  
B'  
When using the IOE for DDR outputs, the two output registers are  
configured to clock two data paths from LEs on rising clock edges. These  
output registers are multiplexed by the clock to drive the output pin at a  
×2 rate. One output register clocks the first bit out on the clock high time,  
while the other output register clocks the second bit out on the clock low  
time. Figure 4–66 shows the IOE configured for DDR output. Figure 4–67  
shows the DDR output timing diagram.  
Altera Corporation  
February 2005  
4–105  
Stratix GX Device Handbook, Volume 1  
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