Stratix GX Architecture
The bus-hold circuitry uses a resistor with a nominal resistance (RBH) of
approximately 7 kΩto weakly pull the signal level to the last-driven state.
The chapter DC & Switching Characteristics of the Stratix GX Device
Handbook, Volume 1 gives the specific sustaining current driven through
this resistor and the overdrive current used to identify the next-driven
input level. This information is provided for each VCCIO voltage level.
The bus-hold circuitry is active only after configuration. When going into
user mode, the bus-hold circuit captures the value on the pin present at
the end of configuration.
Programmable Pull-Up Resistor
Each Stratix GX device I/O pin provides an optional programmable pull-
up resistor during user mode. If this feature is enabled for an I/O pin, the
pull-up resistor (typically 25 kΩ) weakly holds the output to the VCCIO
level of the output pin’s bank. Table 4–26 shows which pin types support
the weak pull-up resistor feature.
Table 4–26. Programmable Weak Pull-Up Resistor Support
Pin Type
Programmable Weak Pull-Up Resistor
I/O pins
v
CLK[15..0]
FCLK
v
FPLL[7..10]CLK
Configuration pins
JTAG pins
v (1)
Note to Table 4–26:
(1) TDO pins do not support programmable weak pull-up resistors.
Advanced I/O Standard Support
Stratix GX device IOEs support the following I/O standards:
■
■
■
■
■
■
■
■
LVTTL
LVCMOS
1.5 V
1.8 V
2.5 V
3.3-V PCI
3.3-V PCI-X 1.0
3.3-V AGP (1× and 2×)
Altera Corporation
February 2005
4–113
Stratix GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
