DC & Switching Characteristics
Table 4–132. Fast PLL Specifications for -7 Speed Grades (Part 2 of 2)
Symbol
Parameter
Min
Max
Unit
tJITTER
tLOCK
m
Period jitter for DIFFIO clock out (6)
Time required for PLL to acquire lock
Multiplication factors for m counter (7)
(5)
100
32
ps
10
1
μs
Integer
Integer
l0, l1, g0
Multiplication factors for l0, l1, and g0
counter (7), (8)
1
32
tARESET
10
ns
Minimum pulse width on areset
signal
Table 4–133. Fast PLL Specifications for -8 Speed Grades (Part 1 of 2)
Symbol
Parameter
CLKINfrequency (1), (3)
Input frequency to PFD
Min
10
Max
460
500
420
Unit
MHz
MHz
MHz
fIN
fINPFD
fOUT
10
Output frequency for internal global or 9.375
regional clock (4)
fOUT_DIFFIO
Output frequency for external clock
driven out on a differential I/O data
channel
(5)
(5)
MHz
fVCO
VCO operating frequency
CLKINduty cycle
300
40
700
60
MHz
%
tINDUTY
tINJITTER
tDUTY
Period jitter for CLKINpin
200
55
ps
Duty cycle for DFFIO1× CLKOUTpin (6) 45
Period jitter for DIFFIO clock out (6)
%
tJITTER
tLOCK
(5)
ps
Time required for PLL to acquire lock
10
1
100
32
μs
m
Multiplication factors for m counter (7)
Integer
Integer
l0, l1, g0
Multiplication factors for l0, l1, and g0
counter (7), (8)
1
32
Altera Corporation
January 2006
4–101
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
