Preliminary Information
Cyclone FPGA Family Data Sheet
Table 70. Cyclone Maximum Output Clock Rate for Row Pins
I/O Standard
-6 Speed
Grade
-7 Speed
Grade
-8 Speed
Grade
Unit
LVTTL
2.5 V
1.8 V
1.5 V
304
220
213
166
304
100
100
134
134
66
304
220
213
166
304
100
100
134
134
66
304
220
213
166
304
100
100
134
134
66
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
LVCMOS
SSTL-3 class I
SSTL-3 class II
SSTL-2 class I
SSTL-2 class II
3.3-V PCI (1)
LVDS
231
231
231
Note to Tables 69 − 70:
(1) EP1C3 devices do not support the PCI I/O standard. These parameters are only
available on row I/O pins.
Cyclone devices are supported by the Altera Quartus II design software,
which provides a comprehensive environment for system-on-a-
programmable-chip (SOPC) design. The Quartus II software includes
HDL and schematic design entry, compilation and logic synthesis, full
simulation and advanced timing analysis, SignalTap II logic analysis, and
device configuration. See the Design Software Selector Guide for more
details on the Quartus II software features.
Software
The Quartus II software supports the Windows 2000/NT/98, Sun Solaris,
Linux Red Hat v7.1 and HP-UX operating systems. It also supports
seamless integration with industry-leading EDA tools through the
NativeLink® interface.
Device pin-outs for Cyclone devices are available on the Altera web site
(http://www.altera.com).
Device Pin-
Outs
Figure 39 describes the ordering codes for Cyclone devices. For more
information on a specific package, refer to the Altera Device Package
Information Data Sheet.
Ordering
Information
Altera Corporation
93
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