Preliminary Information
Cyclone FPGA Family Data Sheet
Table 63. Cyclone I/O Standard Output Delay Adders for Slow Slew Rate on Column Pins (Part 2 of 2)
I/O Standard
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
2.5-V LVTTL
2 mA
3,643
2,446
2,477
2,334
6,606
5,112
4,862
8,380
7,437
6,888
1,799
1,363
2,115
1,820
1,330
4,006
2,690
2,724
2,566
7,267
5,623
5,348
9,218
8,180
7,576
1,979
1,499
2,326
2,001
1,463
4,370
2,934
2,971
2,800
7,927
6,134
5,834
10,055
8,923
8,264
2,158
1,635
2,537
2,183
1,595
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
8 mA
12 mA
16 mA
2 mA
8 mA
12 mA
2 mA
4 mA
8 mA
1.8-V LVTTL
1.5-V LVTTL
SSTL-3 class I
SSTL-3 class II
SSTL-2 class I
SSTL-2 class II
LVDS
Table 64. Cyclone I/O Standard Output Delay Adders for Slow Slew Rate on Row Pins (Part 1 of 2)
I/O Standard -6 Speed Grade -7 Speed Grade -8 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
LVCMOS
2 mA
2,288
1,784
1,320
1,183
2,760
2,395
1,785
1,833
1,655
3,643
2,446
2,477
2,334
2,517
1,962
1,452
1,301
3,036
2,634
1,963
2,016
1,820
4,006
2,690
2,724
2,566
2,745
2,140
1,583
1,419
3,312
2,874
2,142
2,199
1,986
4,370
2,934
2,971
2,800
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
4 mA
8 mA
12 mA
4 mA
3.3-V LVTTL
8 mA
12 mA
16 mA
24 mA
2 mA
2.5-V LVTTL
8 mA
12 mA
16 mA
Altera Corporation
89
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