Cyclone FPGA Family Data Sheet
Preliminary Information
Tables 59 through 64 show the adder delays associated with column and
row I/O pins for all packages. If an I/O standard is selected other than
LVTTL 24 mA with a fast slew rate, add the selected delay to the external
tCO and tSU I/O parameters shown in Tables 44 through 47.
Table 59. Cyclone I/O Standard Column Pin Input Delay Adders
I/O Standard -6 Speed Grade -7 Speed Grade
-8 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
LVCMOS
0
0
0
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
3.3-V LVTTL
2.5-V LVTTL
1.8-V LVTTL
1.5-V LVTTL
SSTL-3 class I
SSTL-3 class II
SSTL-2 class I
SSTL-2 class II
LVDS
0
0
0
28
30
33
214
326
−221
−221
−264
−264
−197
235
358
−244
−244
−291
−291
−217
256
391
−266
−266
−317
−317
−237
Table 60. Cyclone I/O Standard Row Pin Input Delay Adders
I/O Standard -6 Speed Grade -7 Speed Grade
-8 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
LVCMOS
0
0
0
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
3.3-V LVTTL
2.5-V LVTTL
1.8-V LVTTL
1.5-V LVTTL
3.3-V PCI (1)
SSTL-3 class I
SSTL-3 class II
SSTL-2 class I
SSTL-2 class II
LVDS
0
0
0
28
30
33
214
326
0
235
358
0
256
391
0
−221
−221
−264
−264
−197
−244
−244
−291
−291
−217
−266
−266
−317
−317
−237
86
Altera Corporation
ALTERA [ ALTERA CORPORATION ]
