Preliminary Information
Cyclone FPGA Family Data Sheet
Table 66. Cyclone IOE Programmable Delays on Row Pins
Parameter
Setting
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
Decrease input delay to On
3,057
2,212
2,639
3,057
3,057
3,362
2,433
2,902
3,362
3,362
3,668
2,654
3,166
3,668
3,668
ps
ps
ps
ps
ps
internal cells
Small
Medium
Large
Decrease input delay to On
input register
Increase delay to output On
pin
556
611
667
ps
Maximum Input & Output Clock Rates
Tables 67 and 68 show the maximum input clock rate for column and row
pins in Cyclone devices.
Table 67. Cyclone Maximum Input Clock Rate for Column Pins
I/O Standard
-6 Speed
Grade
-7 Speed
Grade
-8 Speed
Grade
Unit
LVTTL
2.5 V
1.8 V
1.5 V
304
220
213
166
304
100
100
134
134
231
304
220
213
166
304
100
100
134
134
231
304
220
213
166
304
100
100
134
134
231
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
LVCMOS
SSTL-3 class I
SSTL-3 class II
SSTL-2 class I
SSTL-2 class II
LVDS
Altera Corporation
91
ALTERA [ ALTERA CORPORATION ]
