Preliminary Information
Cyclone FPGA Family Data Sheet
Table 61. Cyclone I/O Standard Output Delay Adders for Fast Slew Rate on Column Pins
Standard -6 Speed Grade -7 Speed Grade -8 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
LVCMOS
2 mA
1,105
601
137
0
1,216
661
151
0
1,326
721
164
0
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
4 mA
8 mA
12 mA
4 mA
8 mA
12 mA
16 mA
24 mA
2 mA
8 mA
12 mA
16 mA
2 mA
8 mA
12 mA
2 mA
4 mA
8 mA
3.3-V LVTTL
1,105
740
130
178
0
1,216
814
143
196
0
1,326
888
156
213
0
2.5-V LVTTL
1,504
307
338
195
1,062
812
812
2,556
1,613
1,064
616
180
528
233
147
1,654
338
372
214
1,168
893
893
2,812
1,774
1,170
678
198
581
256
162
1,804
368
405
234
1,274
974
974
3,067
1,935
1,276
739
216
633
279
176
1.8-V LVTTL
1.5-V LVTTL
SSTL-3 class I
SSTL-3 class II
SSTL-2 class I
SSTL-2 class II
LVDS
Table 62. Cyclone I/O Standard Output Delay Adders for Fast Slew Rate on Row Pins (Part 1 of 2)
Standard -6 Speed Grade -7 Speed Grade -8 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
LVCMOS
2 mA
1,105
601
137
0
1,216
661
151
0
1,326
721
164
0
ps
ps
ps
ps
4 mA
8 mA
12 mA
Altera Corporation
87
ALTERA [ ALTERA CORPORATION ]
