Cyclone FPGA Family Data Sheet
Preliminary Information
Table 68. Cyclone Maximum Input Clock Rate for Row Pins
I/O Standard
-6 Speed
Grade
-7 Speed
Grade
-8 Speed
Grade
Unit
LVTTL
304
220
213
166
304
100
100
134
134
66
304
220
213
166
304
100
100
134
134
66
304
220
213
166
304
100
100
134
134
66
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
2.5 V
1.8 V
1.5 V
LVCMOS
SSTL-3 class I
SSTL-3 class II
SSTL-2 class I
SSTL-2 class II
3.3-V PCI (1)
LVDS
231
231
231
Note to Tables 67 − 68:
(1) EP1C3 devices do not support the PCI I/O standard. These parameters are only
available on row I/O pins.
Tables 69 and 70 show the maximum output clock rate for column and
row pins in Cyclone devices.
Table 69. Cyclone Maximum Output Clock Rate for Column Pins
I/O Standard
-6 Speed
Grade
-7 Speed
Grade
-8 Speed
Grade
Unit
LVTTL
2.5 V
1.8 V
1.5 V
304
220
213
166
304
100
100
134
134
231
304
220
213
166
304
100
100
134
134
231
304
220
213
166
304
100
100
134
134
231
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
LVCMOS
SSTL-3 class I
SSTL-3 class II
SSTL-2 class I
SSTL-2 class II
LVDS
92
Altera Corporation
ALTERA [ ALTERA CORPORATION ]
