Cyclone FPGA Family Data Sheet
Preliminary Information
Table 62. Cyclone I/O Standard Output Delay Adders for Fast Slew Rate on Row Pins (Part 2 of 2)
Standard -6 Speed Grade -7 Speed Grade -8 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
3.3-V LVTTL
4 mA
1,105
740
1,216
814
1,326
888
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
8 mA
12 mA
16 mA
24 mA
2 mA
130
143
156
178
196
213
0
0
0
2.5-V LVTTL
1,504
307
1,654
338
1,804
368
8 mA
12 mA
16 mA
2 mA
338
372
405
195
214
234
1.8-V LVTTL
1.5-V LVTTL
2,556
1,062
812
2,812
1,168
893
3,067
1,274
974
8 mA
12 mA
2 mA
2,556
1,613
1,064
−8
2,812
1,774
1,170
−9
3,067
1,935
1,276
−10
4 mA
8 mA
3.3-V PCI (1)
SSTL-3 class I
SSTL-3 class II
SSTL-2 class I
SSTL-2 class II
LVDS
616
678
739
180
198
216
528
581
633
233
256
279
147
162
176
Table 63. Cyclone I/O Standard Output Delay Adders for Slow Slew Rate on Column Pins (Part 1 of 2)
I/O Standard
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
LVCMOS
2 mA
2,288
1,784
1,320
1,183
2,760
2,395
1,785
1,833
1,655
2,517
1,962
1,452
1,301
3,036
2,634
1,963
2,016
1,820
2,745
2,140
1,583
1,419
3,312
2,874
2,142
2,199
1,986
ps
ps
ps
ps
ps
ps
ps
ps
ps
4 mA
8 mA
12 mA
4 mA
3.3-V LVTTL
8 mA
12 mA
16 mA
24 mA
88
Altera Corporation
ALTERA [ ALTERA CORPORATION ]
