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EP1C20F400C7ES 参数 Datasheet PDF下载

EP1C20F400C7ES图片预览
型号: EP1C20F400C7ES
PDF下载: 下载PDF文件 查看货源
内容描述: 气旋FPGA系列数据手册 [Cyclone FPGA Family Data Sheet]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 104 页 / 1353 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Cyclone Device Handbook, Volume 1  
Figure 2–31. Control Signal Selection per IOE  
Dedicated I/O  
Clock [5..0]  
io_coe  
Local  
Interconnect  
io_csclr  
Local  
Interconnect  
io_caclr  
Local  
Interconnect  
io_cce_out  
Local  
Interconnect  
io_cce_in  
io_cclk  
Local  
Interconnect  
ce_out  
clk_out  
sclr/preset  
clk_in  
ce_in  
aclr/preset  
oe  
Local  
Interconnect  
In normal bidirectional operation, you can use the input register for input  
data requiring fast setup times. The input register can have its own clock  
input and clock enable separate from the OE and output registers. The  
output register can be used for data requiring fast clock-to-output  
performance. The OE register is available for fast clock-to-output enable  
timing. The OE and output register share the same clock source and the  
same clock enable source from the local interconnect in the associated  
LAB, dedicated I/O clocks, or the column and row interconnects.  
Figure 2–32 shows the IOE in bidirectional configuration.  
2–44  
Preliminary  
Altera Corporation  
January 2007  
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