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EP1C20F400C7ES 参数 Datasheet PDF下载

EP1C20F400C7ES图片预览
型号: EP1C20F400C7ES
PDF下载: 下载PDF文件 查看货源
内容描述: 气旋FPGA系列数据手册 [Cyclone FPGA Family Data Sheet]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 104 页 / 1353 K
品牌: ALTERA [ ALTERA CORPORATION ]
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I/O Structure  
The pin's datain signals can drive the logic array. The logic array drives  
the control and data signals, providing a flexible routing resource. The  
row or column IOE clocks, io_clk[5..0], provide a dedicated routing  
resource for low-skew, high-speed clocks. The global clock network  
generates the IOE clocks that feed the row or column I/O regions (see  
“Global Clock Network & Phase-Locked Loops” on page 2–29).  
Figure 2–30 illustrates the signal paths through the I/O block.  
Figure 2–30. Signal Path through the I/O Block  
Row or Column  
io_clk[5..0]  
To Other  
IOEs  
io_datain  
To Logic  
Array  
comb_io_datain  
oe  
ce_in  
io_csclr  
io_coe  
ce_out  
aclr/preset  
sclr  
Data and  
Control  
Signal  
IOE  
io_cce_in  
io_cce_out  
Selection  
From Logic  
Array  
clk_in  
io_caclr  
io_cclk  
clk_out  
dataout  
io_dataout  
Each IOE contains its own control signal selection for the following  
control signals: oe, ce_in, ce_out, aclr/preset, sclr/preset,  
clk_in, and clk_out. Figure 2–31 illustrates the control signal  
selection.  
Altera Corporation  
January 2007  
2–43  
Preliminary  
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