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EP1C20F400C7ES 参数 Datasheet PDF下载

EP1C20F400C7ES图片预览
型号: EP1C20F400C7ES
PDF下载: 下载PDF文件 查看货源
内容描述: 气旋FPGA系列数据手册 [Cyclone FPGA Family Data Sheet]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 104 页 / 1353 K
品牌: ALTERA [ ALTERA CORPORATION ]
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I/O Structure  
Figure 2–32. Cyclone IOE in Bidirectional I/O Configuration  
ioe_clk[5..0]  
Column or Row  
Interconect  
OE  
OE Register  
PRN  
D
Q
V
CCIO  
clkout  
ENA  
Optional  
PCI Clamp  
CLRN  
ce_out  
V
CCIO  
Programmable  
Pull-Up  
aclr/prn  
Resistor  
Chip-Wide Reset  
Output Register  
Output  
Pin Delay  
PRN  
D
Q
ENA  
Drive Strength Control  
Open-Drain Output  
Slew Control  
sclr/preset  
CLRN  
comb_datain  
Input Pin to  
Logic Array Delay  
data_in  
Bus Hold  
Input Pin to  
Input Register Delay  
or Input Pin to  
Input Register  
PRN  
Logic Array Delay  
D
Q
ENA  
clkin  
CLRN  
ce_in  
The Cyclone device IOE includes programmable delays to ensure zero  
hold times, minimize setup times, or increase clock to output times.  
A path in which a pin directly drives a register may require a  
programmable delay to ensure zero hold time, whereas a path in which a  
pin drives a register through combinatorial logic may not require the  
delay. Programmable delays decrease input-pin-to-logic-array and IOE  
input register delays. The Quartus II Compiler can program these delays  
Altera Corporation  
January 2007  
2–45  
Preliminary  
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