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EP1C20F400C7ES 参数 Datasheet PDF下载

EP1C20F400C7ES图片预览
型号: EP1C20F400C7ES
PDF下载: 下载PDF文件 查看货源
内容描述: 气旋FPGA系列数据手册 [Cyclone FPGA Family Data Sheet]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 104 页 / 1353 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Cyclone Device Handbook, Volume 1  
Table 2–10. DQ Pin Groups (Part 2 of 2)  
Number of × 8 DQ  
Total DQ Pin  
Count  
Device  
Package  
Pin Groups  
EP1C6  
144-pin TQFP  
4
4
4
4
4
8
8
8
32  
32  
32  
32  
32  
64  
64  
64  
240-pin PQFP  
256-pin FineLine BGA  
240-pin PQFP  
EP1C12  
EP1C20  
256-pin FineLine BGA  
324-pin FineLine BGA  
324-pin FineLine BGA  
400-pin FineLine BGA  
Note to Table 2–10:  
(1) EP1C3 devices in the 100-pin TQFP package do not have any DQ pin groups in  
I/O bank 1.  
A programmable delay chain on each DQS pin allows for either a 90°  
phase shift (for DDR SDRAM), or a 72° phase shift (for FCRAM) which  
automatically center-aligns input DQS synchronization signals within the  
data window of their corresponding DQ data signals. The phase-shifted  
DQS signals drive the global clock network. This global DQS signal clocks  
DQ signals on internal LE registers.  
These DQS delay elements combine with the PLL’s clocking and phase  
shift ability to provide a complete hardware solution for interfacing to  
high-speed memory.  
The clock phase shift allows the PLL to clock the DQ output enable and  
output paths. The designer should use the following guidelines to meet  
133 MHz performance for DDR SDRAM and FCRAM interfaces:  
The DQS signal must be in the middle of the DQ group it clocks  
Resynchronize the incoming data to the logic array clock using  
successive LE registers or FIFO buffers  
LE registers must be placed in the LAB adjacent to the DQ I/O pin  
column it is fed by  
Figure 2–34 illustrates DDR SDRAM and FCRAM interfacing from the  
I/O through the dedicated circuitry to the logic array.  
2–48  
Preliminary  
Altera Corporation  
January 2007  
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