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EP1C20F400C7ES 参数 Datasheet PDF下载

EP1C20F400C7ES图片预览
型号: EP1C20F400C7ES
PDF下载: 下载PDF文件 查看货源
内容描述: 气旋FPGA系列数据手册 [Cyclone FPGA Family Data Sheet]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 104 页 / 1353 K
品牌: ALTERA [ ALTERA CORPORATION ]
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I/O Structure  
output pins (nSTATUSand CONF_DONE) and all the JTAG pins in I/O  
bank 3 must operate at 2.5 V because the VCCIO level of SSTL-2 is 2.5 V.  
I/O banks 1, 2, 3, and 4 support DQS signals with DQ bus modes of × 8.  
For × 8 mode, there are up to eight groups of programmable DQS and DQ  
pins, I/O banks 1, 2, 3, and 4 each have two groups in the 324-pin and  
400-pin FineLine BGA packages. Each group consists of one DQS pin, a  
set of eight DQ pins, and one DM pin (see Figure 2–33). Each DQS pin  
drives the set of eight DQ pins within that group.  
Figure 2–33. Cyclone Device DQ & DQS Groups in × 8 Mode  
Note (1)  
Top, Bottom, Left, or Right I/O Bank  
DQ Pins  
DQS Pin  
DM Pin  
Note to Figure 2–33:  
(1) Each DQ group consists of one DQS pin, eight DQ pins, and one DM pin.  
Table 2–10 shows the number of DQ pin groups per device.  
Table 2–10. DQ Pin Groups (Part 1 of 2)  
Number of × 8 DQ  
Total DQ Pin  
Device  
Package  
Pin Groups  
Count  
EP1C3  
100-pin TQFP (1)  
144-pin TQFP  
3
4
8
8
24  
32  
64  
64  
EP1C4  
324-pin FineLine BGA  
400-pin FineLine BGA  
Altera Corporation  
January 2007  
2–47  
Preliminary  
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