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EP1C20F400C7ES 参数 Datasheet PDF下载

EP1C20F400C7ES图片预览
型号: EP1C20F400C7ES
PDF下载: 下载PDF文件 查看货源
内容描述: 气旋FPGA系列数据手册 [Cyclone FPGA Family Data Sheet]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 104 页 / 1353 K
品牌: ALTERA [ ALTERA CORPORATION ]
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I/O Structure  
IOEs support many features, including:  
I/O Structure  
Differential and single-ended I/O standards  
3.3-V, 64- and 32-bit, 66- and 33-MHz PCI compliance  
Joint Test Action Group (JTAG) boundary-scan test (BST) support  
Output drive strength control  
Weak pull-up resistors during configuration  
Slew-rate control  
Tri-state buffers  
Bus-hold circuitry  
Programmable pull-up resistors in user mode  
Programmable input and output delays  
Open-drain outputs  
DQ and DQS I/O pins  
Cyclone device IOEs contain a bidirectional I/O buffer and three registers  
for complete embedded bidirectional single data rate transfer.  
Figure 2–27 shows the Cyclone IOE structure. The IOE contains one input  
register, one output register, and one output enable register. You can use  
the input registers for fast setup times and output registers for fast clock-  
to-output times. Additionally, you can use the output enable (OE) register  
for fast clock-to-output enable timing. The Quartus II software  
automatically duplicates a single OE register that controls multiple  
output or bidirectional pins. IOEs can be used as input, output, or  
bidirectional pins.  
Altera Corporation  
January 2007  
2–39  
Preliminary  
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