Chapter 4: DC and Switching Characteristics
4–103
PLL Timing Specifications
PLL Timing Specifications
Table 4–116 and Table 4–117 describe the Arria GX PLL specifications when operating
in both the commercial junction temperature range (0 to 85 C) and the industrial
junction temperature range (–40 to 100 C), except for the clock switchover and
phase-shift stepping features. These two features are only supported from the 0 to
100 C junction temperature range.
Table 4–116. Enhanced PLL Specifications (Part 1 of 2)
Name Description
Input clock frequency
Min
2
Typ
—
—
—
—
Max
500
420
60
Units
MHz
MHz
%
fIN
fINPFD
fINDUTY
fENDUTY
Input frequency to the PFD
2
Input clock duty cycle
40
40
External feedback input clock duty cycle
60
%
Input or external feedback clock input jitter
tolerance in terms of period jitter.
—
—
0.5
1.0
—
—
ns (peak-to-peak)
ns (peak-to-peak)
Bandwidth 0.85 MHz
tINJITTER
Input or external feedback clock input jitter
tolerance in terms of period jitter.
Bandwidth 0.85 MHz
tOUTJITTER
tFCOMP
Dedicated clock output period jitter
External feedback compensation time
50
—
100
—
250
10
ps (p-p)
ns
Output frequency for internal global or regional
clock
fOUT
1.5 (2)
—
—
—
550
100
—
MHz
MHz
ns
fSCANCLK
tCONFIGEPLL
Scanclk frequency
Time required to reconfigure scan chains for
EPLLs
—
174/fSCANCLK
fOUT_EXT
fOUTDUTY
PLL external clock output frequency
Duty cycle for external clock output
1.5 (2)
(1)
MHz
%
45
50
55
Time required for the PLL to lock from the time
it is enabled or the end of device configuration
tLOCK
—
0.03
1
ms
Time required for the PLL to lock dynamically
after automatic clock switchover between two
identical clock frequencies
tDLOCK
—
—
1
1
ms
Frequency range where the clock switchover
performs properly
fSWITCHOVER
1.5
500
MHz
fCLBW
fVCO
fSS
PLL closed-loop bandwidth
0.13
300
100
1.2
—
—
16.9
840
500
MHz
MHz
kHz
PLL VCO operating range
Spread-spectrum modulation frequency
Percent down spread for a given clock
frequency
% spread
0.4
0.5
0.6
%
tPLL_PSERR
tARESET
Accuracy of PLL phase shift
—
10
—
—
30
—
ps
ns
Minimum pulse width on aresetsignal.
Minimum pulse width on the aresetsignal
when using PLL reconfiguration. Reset the PLL
after scandonegoes high.
tARESET_RECONFIG
500
—
—
ns
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
