Chapter 4: DC and Switching Characteristics
4–99
Duty Cycle Distortion
Table 4–110. Maximum DCD for DDIO Output on Row I/O Pins Without PLL in the Clock Path Note (1)
Input I/O Standard (No PLL in the Clock Path)
Maximum DCD (ps) for
Row DDIO Output I/O
Standard
TTL/CMOS
SSTL-2
SSTL/HSTL
LVDS
Units
3.3/2.5V
180
1.8/1.5V
2.5V
1.8/1.5V
3.3V
LVDS
180
180
180
180
ps
Note to Table 4–110:
(1) Table 4–110 assumes the input clock has zero DCD.
Table 4–111. Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path
(Note 1)
Input IO Standard (No PLL in the Clock Path)
Maximum DCD (ps) for
DDIO Column Output I/O
Standard
TTL/CMOS
SSTL-2
SSTL/HSTL
Units
3.3/2.5V
440
390
375
325
430
355
350
335
320
330
330
330
330
180
1.8/1.5V
495
450
430
385
490
410
405
390
375
385
385
390
360
180
2.5V
170
120
105
90
1.8/1.5V
160
110
95
3.3-V LVTTL
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
3.3-V LVCMOS
2.5 V
1.8 V
100
155
75
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
LVPECL
160
85
80
70
65
65
70
80
60
70
60
70
60
70
90
100
180
180
Note to Table 4–111:
(1) Table 4–111 assumes the input clock has zero DCD.
Table 4–112. Maximum DCD for DDIO Output on Row I/O Pins With PLL in the Clock Path
Arria GX Devices (PLL Output
Feeding DDIO)
Maximum DCD (ps) for Row DDIO Output I/O Standard
Units
–6 Speed Grade
3.3-V LVTTL
3.3-V LVCMOS
2.5V
105
75
ps
ps
ps
ps
ps
ps
ps
90
1.8V
100
100
75
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
70
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
