4–102
Chapter 4: DC and Switching Characteristics
High-Speed I/O Specifications
Table 4–115. High-Speed I/O Specifications (Part 2 of 2)Note (1), (2)
–6 Speed Grade
Units
Symbol
Conditions
Min
Typ
Max
Standard
SPI-4
Training Pattern
Transition
Density
—
—
000000000011
11111111
10%
256
—
—
Number of
repetitions
DPA lock time
Parallel Rapid
I/O
00001111
10010000
10101010
01010101
25%
50%
100%
—
256
256
256
256
—
—
—
—
—
—
—
—
Miscellaneous
Notes to Table 4–115:
(1) When J = 4 to 10, the SERDES block is used.
(2) When J = 1 or 2, the SERDES block is bypassed.
(3) The input clock frequency and the W factor must satisfy the following fast PLL VCO specification: 150 input clock frequency × W 1,040.
(4) The minimum specification is dependent on the clock source (fast PLL, enhanced PLL, clock pin, and so on) and the clock routing resource
(global, regional, or local) used. The I/O differential buffer and input register do not have a minimum toggle rate.
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
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