4–106
Chapter 4: DC and Switching Characteristics
JTAG Timing Specifications
Table 4–121. DQS Bus Clock Skew Adder Specifications (tDQS_CLOCK_SKEW_ADDER
)
Mode
DQS Clock Skew Adder (ps)
4 DQ per DQS
9 DQ per DQS
18 DQ per DQS
36 DQ per DQS
40
70
75
95
Table 4–122. DQS Phase Offset Delay Per Stage (ps) Note (1), (2), (3)
Positive Offset
Negative Offset
Speed Grade
Min
Max
Min
Max
–6
10
16
8
12
Notes to Table 4–122:
(1) The delay settings are linear.
(2) The valid settings for phase offset are –32 to +31.
(3) The typical value equals the average of the minimum and maximum values.
JTAG Timing Specifications
Figure 4–13 shows the timing requirements for the JTAG signals
Figure 4–13. Arria GX JTAG Waveforms.
TMS
TDI
tJCP
tJCH
t JCL
tJPH
tJPSU
TCK
TDO
tJPXZ
tJPZX
tJPCO
tJSSU
tJSH
Signal
to be
Captured
tJSCO
tJSZX
tJSXZ
Signal
to be
Driven
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
