Chapter 4: DC and Switching Characteristics
4–105
External Memory Interface Specifications
Table 4–117. Fast PLL Specifications (Part 2 of 2)
Name
Description
Min
Typ
Max
Units
Minimum pulse width
on the aresetsignal
when using PLL
reconfiguration. Reset
the PLL after
tARESET_RECONFIG
500
—
—
ns
scandonegoes high.
Note to Table 4–117:
(1) This is limited by the I/O fMAX
.
External Memory Interface Specifications
Table 4–118 through Table 4–122 list Arria GX device specifications for the dedicated
circuitry used for interfacing with external memory devices.
Table 4–118. DLL Frequency Range Specifications
Frequency Mode
Frequency Range (MHz)
100 to 175
0
1
2
150 to 230
200 to 310
Table 4–119. DQS Jitter Specifications for DLL-Delayed Clock (tDQS_JITTER) , (Note 1)
Number of DQS Delay Buffer Stages (2)
Commercial (ps)
Industrial (ps)
1
80
110
130
180
210
2
110
130
160
3
4
Notes to Table 4–119:
(1) Peak-to-peak period jitter on the phase-shifted DQS clock. For example, jitter on two delay stages under
commercial conditions is 200 ps peak-to-peak or 100 ps.
(2) Delay stages used for requested DQS phase shift are reported in a project’s Compilation Report in the Quartus II
software.
Table 4–120. DQS Phase-Shift Error Specifications for DLL-Delayed Clock (tDQS_PSERR
)
Number of DQS Delay Buffer Stages
–6 Speed Grade (ps)
1
2
3
4
35
70
105
140
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
