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EP1AGX 参数 Datasheet PDF下载

EP1AGX图片预览
型号: EP1AGX
PDF下载: 下载PDF文件 查看货源
内容描述: 第一节的Arria GX器件数据手册 [Section I. Arria GX Device Data Sheet]
分类和应用:
文件页数/大小: 234 页 / 3509 K
品牌: ALTERA [ ALTERA CORPORATION ]
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4–104  
Chapter 4: DC and Switching Characteristics  
PLL Timing Specifications  
Table 4–116. Enhanced PLL Specifications (Part 2 of 2)  
Name  
Description  
Min  
Typ  
Max  
Units  
The time required for the wait after the  
reconfiguration is done and the areset is  
applied.  
tRECONFIGWAIT  
2
us  
Notes to Table 4–116:  
(1) This is limited by the I/O fMAX  
.
(2) If the counter cascading feature of the PLL is used, there is no minimum output clock frequency.  
Table 4–117. Fast PLL Specifications (Part 1 of 2)  
Name  
Description  
Min  
Typ  
Max  
Units  
fIN  
Input clock frequency  
16.08  
640  
MHz  
Input frequency to the  
PFD  
fINPFD  
fINDUTY  
16.08  
40  
500  
60  
MHz  
%
Input clock duty cycle  
Input clock jitter  
tolerance in terms of  
period jitter.  
0.5  
1.0  
ns (p-p)  
ns (p-p)  
Bandwidth 2 MHz  
tINJITTER  
Input clock jitter  
tolerance in terms of  
period jitter.  
Bandwidth 0.2 MHz  
Upper VCO frequency  
range  
300  
150  
840  
420  
550  
840  
MHz  
MHz  
MHz  
MHz  
fVCO  
Lower VCO frequency  
range  
PLL output frequency  
to GCLKor RCLK  
4.6875  
150  
fOUT  
PLL output frequency  
to LVDS or DPA clock  
PLL clock output  
frequency to regular  
I/O  
fOUT_EXT  
4.6875  
(1)  
MHz  
Time required to  
reconfigure scan  
chains for fast PLLs  
tCONFIGPLL  
75/fSCANCLK  
28  
ns  
PLL closed-loop  
bandwidth  
fCLBW  
1.16  
5
MHz  
Time required for the  
PLL to lock from the  
time it is enabled or  
the end of the device  
configuration  
tLOCK  
0.03  
1
ms  
Accuracy of PLL phase  
shift  
tPLL_PSERR  
tARESET  
10  
30  
ps  
ns  
Minimum pulse width  
on aresetsignal.  
Arria GX Device Handbook, Volume 1  
© December 2009 Altera Corporation