Chapter 4: DC and Switching Characteristics
4–107
JTAG Timing Specifications
Table 4–123 lists the JTAG timing parameters and values for Arria GX devices.
Table 4–123. Arria GX JTAG Timing Parameters and Values
Symbol Parameter
tJCP TCK clock period
Min
30
12
12
4
Max
—
—
—
—
—
9
Units
ns
ns
ns
ns
ns
ns
ns
tJCH
TCK clock high time
tJCL
TCK clock low time
tJPSU
tJPH
JTAG port setup time
JTAG port hold time
5
tJPCO
tJPZX
tJPXZ
tJSSU
tJSH
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Capture register setup time
Capture register hold time
Update register clock to output
—
—
—
4
9
9
ns
—
—
12
ns
ns
ns
5
tJSCO
—
Update register high impedance to valid
output
tJSZX
tJSXZ
—
—
12
12
ns
ns
Update register valid output to high
impedance
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
