4–98
Chapter 4: DC and Switching Characteristics
Duty Cycle Distortion
To calculate the DCD as a percentage:
(T/2 – DCD) / T = (3,745 ps/2 – 125 ps) / 3,745 ps = 46.66% (for low boundary)
(T/2 + DCD) / T = (3,745 ps/2 + 125 ps) / 3,745 ps = 53.33% (for high boundary)
Therefore, the DCD percentage for the output clock at 267 MHz is from 46.66% to
53.33%.
Table 4–109. Maximum DCD for Non-DDIO Output on Column I/O Pins
Maximum DCD (ps)
for Non-DDIO Output
Column I/O Output Standard I/O Standard
Units
–6 Speed Grade
3.3-V LVTTL
220
175
155
110
215
135
130
115
100
110
110
115
80
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
3.3-V LVCMOS
2.5 V
1.8 V
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.2-V HSTL-12
LVPECL
200
80
Table 4–110. Maximum DCD for DDIO Output on Row I/O Pins Without PLL in the Clock Path Note (1)
Input I/O Standard (No PLL in the Clock Path)
Maximum DCD (ps) for
Row DDIO Output I/O
Standard
TTL/CMOS
SSTL-2
SSTL/HSTL
LVDS
Units
3.3/2.5V
1.8/1.5V
495
2.5V
170
120
105
90
1.8/1.5V
160
110
95
3.3V
105
75
3.3-V LVTTL
440
390
375
325
430
355
350
335
330
330
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
3.3-V LVCMOS
2.5 V
450
430
90
1.8 V
385
100
155
75
135
100
85
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
1.8-V HSTL Class I
1.5-V HSTL Class I
490
160
85
410
405
80
70
90
390
65
65
105
110
105
385
60
70
390
60
70
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
