欢迎访问ic37.com |
会员登录 免费注册
发布采购

EP1AGX50DF780C6 参数 Datasheet PDF下载

EP1AGX50DF780C6图片预览
型号: EP1AGX50DF780C6
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 50160 CLBs, 640MHz, PBGA780, 29 X 29 MM, 1 MM PITCH, FBGA-780]
分类和应用: 现场可编程门阵列可编程逻辑LTE时钟
文件页数/大小: 296 页 / 3505 K
品牌: ALTERA [ ALTERA CORPORATION ]
 浏览型号EP1AGX50DF780C6的Datasheet PDF文件第79页浏览型号EP1AGX50DF780C6的Datasheet PDF文件第80页浏览型号EP1AGX50DF780C6的Datasheet PDF文件第81页浏览型号EP1AGX50DF780C6的Datasheet PDF文件第82页浏览型号EP1AGX50DF780C6的Datasheet PDF文件第84页浏览型号EP1AGX50DF780C6的Datasheet PDF文件第85页浏览型号EP1AGX50DF780C6的Datasheet PDF文件第86页浏览型号EP1AGX50DF780C6的Datasheet PDF文件第87页  
Arria GX Architecture  
Modes of Operation  
The adder, subtractor, and accumulate functions of a DSP block have four  
modes of operation:  
Simple multiplier  
Multiply-accumulator  
Two-multipliers adder  
Four-multipliers adder  
Table 2–14 shows the different number of multipliers possible in each  
DSP block mode according to size. These modes allow the DSP blocks to  
implement numerous applications for DSP including FFTs, complex FIR,  
FIR, 2D FIR filters, equalizers, IIR, correlators, matrix multiplication, and  
many other functions. DSP blocks also support mixed modes and mixed  
multiplier sizes in the same block. For example, half of one DSP block can  
implement one 18 × 18-bit multiplier in multiply-accumulator mode,  
while the other half of the DSP block implements four 9 × 9-bit multipliers  
in simple multiplier mode.  
Table 2–14. Multiplier Size and Configurations per DSP Block  
DSP Block Mode  
9 × 9  
18 × 18  
36 × 36  
Multiplier  
Eight multipliers with  
eight product outputs  
Four multipliers with four One multiplier with one  
product outputs  
product output  
Multiply-accumulator  
Two-multipliers adder  
Two 52-bit multiply-  
accumulate blocks  
Four two-multiplier adder Two two-multiplier adder  
(two 9 × 9 complex  
multiply)  
(one 18 × 18 complex  
multiply)  
Four-multipliers adder  
Two four-multiplier adder One four-multiplier adder  
DSP Block Interface  
The Arria GX device DSP block input registers can generate a shift  
register that can cascade down in the same DSP block column. Dedicated  
connections between DSP blocks provide fast connections between shift  
register inputs to cascade shift register chains. You can cascade registers  
within multiple DSP blocks for 9 × 9- or 18 × 18-bit FIR filters larger than  
four taps, with additional adder stages implemented in ALMs. If the DSP  
block is configured as 36 × 36 bits, the adder, subtractor, or accumulator  
stages are implemented in ALMs. Each DSP block can route the shift  
register chain out of the block to cascade multiple columns of DSP blocks.  
Altera Corporation  
May 2008  
2–75  
Arria GX Device Handbook, Volume 1  
 复制成功!