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EP1AGX50DF780C6 参数 Datasheet PDF下载

EP1AGX50DF780C6图片预览
型号: EP1AGX50DF780C6
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 50160 CLBs, 640MHz, PBGA780, 29 X 29 MM, 1 MM PITCH, FBGA-780]
分类和应用: 现场可编程门阵列可编程逻辑LTE时钟
文件页数/大小: 296 页 / 3505 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Digital Signal Processing Block  
The DSP block is divided into four block units that interface with four  
LAB rows on the left and right. Each block unit can be considered one  
complete 18 × 18-bit multiplier with 36 inputs and 36 outputs. A local  
interconnect region is associated with each DSP block. Like a LAB, this  
interconnect region can be fed with 16 direct link interconnects from the  
LAB to the left or right of the DSP block in the same row. R4 and C4  
routing resources can access the DSP block’s local interconnect region.  
The outputs also work similarly to LAB outputs as well. Eighteen outputs  
from the DSP block can drive to the left LAB through direct link  
interconnects and 18 can drive to the right LAB though direct link  
interconnects. All 36 outputs can drive to R4 and C4 routing  
interconnects. Outputs can drive right- or left-column routing.  
2–76  
Arria GX Device Handbook, Volume 1  
Altera Corporation  
May 2008  
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