Digital Signal Processing Block
Figure 2–51. DSP Block Diagram for 18 × 18-Bit Configuration
Optional Serial Shift Register
Inputs from Previous
DSP Block
Multiplier Stage
Optional Stage Configurable
as Accumulator or Dynamic
Adder/Subtractor
Output Selection
Multiplexer
D
Q
ENA
CLRN
D
Q
ENA
CLRN
D
Q
ENA
CLRN
Adder/
Subtractor/
Accumulator
1
D
Q
ENA
CLRN
D
Q
ENA
CLRN
D
Q
ENA
CLRN
Summation
D
Q
ENA
CLRN
D
Q
Optional Output
Register Stage
Summation Stage
for Adding Four
ENA
CLRN
D
Q
Multipliers Together
ENA
CLRN
Adder/
Subtractor/
Accumulator
2
D
Q
ENA
CLRN
D
Q
Optional Serial
Shift Register
Outputs to
Optional Pipeline
Register Stage
ENA
Next DSP Block
in the Column
CLRN
D
Q
ENA
CLRN
Optional Input Register
Stage with Parallel Input or
Shift Register Configuration
to MultiTrack
Interconnect
2–74
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
ALTERA [ ALTERA CORPORATION ]
