Arria GX Architecture
Table 2–8. Available Clocking Connections for Transceivers in EP1AGX60E and EP1AGX90E
Clock Resource
Transceiver
Source
Regional
Clock
Bank13
8 Clock I/O
Bank14
8 Clock I/O
Bank15
8 Clock I/O
Global Clock
Region0
8 LRIO clock
RCLK 20-27
v
v
v
v
v
v
Region1
8 LRIO clock
RCLK 20-27
RCLK 12-19
RCLK 12-19
v
v
Region2
8 LRIO clock
v
v
Region3
8 LRIO clock
Each logic array block (LAB) consists of eight adaptive logic modules
(ALMs), carry chains, shared arithmetic chains, LAB control signals, local
interconnects, and register chain connection lines. The local interconnect
transfers signals between ALMs in the same LAB. Register chain
connections transfer the output of an ALM register to the adjacent ALM
register in a LAB. The Quartus II Compiler places associated logic in a
LAB or adjacent LABs, allowing the use of local, shared arithmetic chain,
and register chain connections for performance and area efficiency.
Table 2–9 shows Arria GX device resources. Figure 2–25 shows the
Arria GX LAB structure.
Logic Array
Blocks
Table 2–9. Arria GX Device Resources
M512 RAM
Columns/Blocks Columns/Blocks
M4K RAM
M-RAM
Blocks
DSP Block
Columns/Blocks
Device
EP1AGX20
EP1AGX35
EP1AGX50
EP1AGX60
EP1AGX90
166
197
313
326
478
118
140
242
252
400
1
1
2
2
4
10
14
26
32
44
Altera Corporation
May 2008
2–35
Arria GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
