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EP1AGX50DF780C6 参数 Datasheet PDF下载

EP1AGX50DF780C6图片预览
型号: EP1AGX50DF780C6
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 50160 CLBs, 640MHz, PBGA780, 29 X 29 MM, 1 MM PITCH, FBGA-780]
分类和应用: 现场可编程门阵列可编程逻辑LTE时钟
文件页数/大小: 296 页 / 3505 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Transceivers  
Figure 2–22 shows the input reference clock sources for the transmitter  
and receiver PLL.  
Figure 2–22. Input Reference Clock Sources  
Inter-Transceiver Lines [2]  
Transceiver Block 2  
Transceiver Block 1  
Inter-Transceiver Lines [1]  
Inter-Transceiver Lines [0]  
Transceiver Block 0  
Dedicated  
REFCLK0  
/2  
/2  
Transmitter  
PLL  
Dedicated  
REFCLK1  
Inter-Transceiver Lines [2:0]  
Global Clock (1)  
Four  
Receiver  
PLLs  
Global Clock (1)  
f
For detailed transceiver clocking in all supported functional modes, refer  
to the Arria GX Transceiver Architecture chapter in volume 2 of the  
Arria GX Device Handbook.  
PLD Clock Utilization by Transceiver Blocks  
Arria GX devices have up to 16 global clock (GCLK) lines and 16 regional  
clock (RCLK) lines that are used to route the transceiver clocks. The  
following transceiver clocks utilize the available global and regional clock  
resources:  
pll_inclk(if driven from an FPGA input pin)  
rx_cruclk(if driven from an FPGA input pin)  
tx_clkout/coreclkout(CMU low-speed parallel clock  
forwarded to the PLD)  
Recovered clock from each channel (rx_clkout) in non-rate  
matcher mode  
2–32  
Arria GX Device Handbook, Volume 1  
Altera Corporation  
May 2008  
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