Transceivers
Figure 2–22 shows the input reference clock sources for the transmitter
and receiver PLL.
Figure 2–22. Input Reference Clock Sources
Inter-Transceiver Lines [2]
Transceiver Block 2
Transceiver Block 1
Inter-Transceiver Lines [1]
Inter-Transceiver Lines [0]
Transceiver Block 0
Dedicated
REFCLK0
/2
/2
Transmitter
PLL
Dedicated
REFCLK1
Inter-Transceiver Lines [2:0]
Global Clock (1)
Four
Receiver
PLLs
Global Clock (1)
f
For detailed transceiver clocking in all supported functional modes, refer
to the Arria GX Transceiver Architecture chapter in volume 2 of the
Arria GX Device Handbook.
PLD Clock Utilization by Transceiver Blocks
Arria GX devices have up to 16 global clock (GCLK) lines and 16 regional
clock (RCLK) lines that are used to route the transceiver clocks. The
following transceiver clocks utilize the available global and regional clock
resources:
■
■
■
pll_inclk(if driven from an FPGA input pin)
rx_cruclk(if driven from an FPGA input pin)
tx_clkout/coreclkout(CMU low-speed parallel clock
forwarded to the PLD)
■
Recovered clock from each channel (rx_clkout) in non-rate
matcher mode
2–32
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008