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EP1AGX50DF780C6 参数 Datasheet PDF下载

EP1AGX50DF780C6图片预览
型号: EP1AGX50DF780C6
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 50160 CLBs, 640MHz, PBGA780, 29 X 29 MM, 1 MM PITCH, FBGA-780]
分类和应用: 现场可编程门阵列可编程逻辑LTE时钟
文件页数/大小: 296 页 / 3505 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Logic Array Blocks  
Figure 2–25. Arria GX LAB Structure  
Row Interconnects of  
Variable Speed & Length  
ALMs  
Direct link  
interconnect from  
adjacent block  
Direct link  
interconnect from  
adjacent block  
Direct link  
Direct link  
interconnect to  
adjacent block  
interconnect to  
adjacent block  
Local Interconnect  
LAB  
Local Interconnect is Driven  
from Either Side by Columns & LABs,  
& from Above by Rows  
Column Interconnects of  
Variable Speed & Length  
LAB Interconnects  
The LAB local interconnect can drive all eight ALMs in the same LAB. It  
is driven by column and row interconnects and ALM outputs in the same  
LAB. Neighboring LABs, M512 RAM blocks, M4K RAM blocks, M-RAM  
blocks, or digital signal processing (DSP) blocks from the left and right  
can also drive a LAB's local interconnect through the direct link  
connection. The direct link connection feature minimizes the use of row  
and column interconnects, providing higher performance and flexibility.  
Each ALM can drive 24 ALMs through fast local and direct link  
interconnects.  
2–36  
Arria GX Device Handbook, Volume 1  
Altera Corporation  
May 2008  
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