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EP1AGX50DF780C6 参数 Datasheet PDF下载

EP1AGX50DF780C6图片预览
型号: EP1AGX50DF780C6
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 50160 CLBs, 640MHz, PBGA780, 29 X 29 MM, 1 MM PITCH, FBGA-780]
分类和应用: 现场可编程门阵列可编程逻辑LTE时钟
文件页数/大小: 296 页 / 3505 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Transceivers  
Figure 2–24. Regional Clock Resources in Arria GX Devices  
CLK[15..12]  
11 5  
7
RCLK  
RCLK  
[31..28]  
[27..24]  
Arria GX  
Transceiver  
Block  
RCLK  
[3..0]  
RCLK  
[23..20]  
1
2
CLK[3..0]  
RCLK  
[7..4]  
RCLK  
[19..16]  
Arria GX  
Transceiver  
Block  
RCLK  
[11..8]  
RCLK  
[15..12]  
8
12 6  
CLK[7..4]  
For the regional or global clock network to route into the transceiver, a  
local route input output (LRIO) channel is required. Each LRIO clock  
region has up to eight clock paths and each transceiver block has a  
maximum of eight clock paths for connecting with LRIO clocks. These  
resources are limited and determine the number of clocks that can be used  
between the PLD and transceiver blocks. Tables 2–7 and 2–8 give the  
number of LRIO resources available for Arria GX devices with different  
number of transceiver blocks.  
Table 2–7. Available Clocking Connections for Transceivers in EP1AGX35D,  
EP1AGX50D, and EP1AGX60D  
Clock Resource  
Transceiver  
Source  
Regional  
Clock  
Bank13  
8 Clock I/O  
Bank14  
8 Clock I/O  
Global Clock  
Region0  
8 LRIO clock  
RCLK 20-27  
v
v
v
Region1  
8 LRIO clock  
RCLK 12-19  
v
2–34  
Arria GX Device Handbook, Volume 1  
Altera Corporation  
May 2008  
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