Arria GX Architecture
Transceiver Clocking
This section describes the clock distribution within an Arria GX
transceiver channel and the PLD clock resource utilization by the
transceiver blocks.
Transceiver Channel Clock Distribution
Each transceiver block has one transmitter PLL and four receiver PLLs.
The transmitter PLL multiplies the input reference clock to generate a
high-speed serial clock at a frequency that is half the data rate of the
configured functional mode. This high-speed serial clock (or its
divide-by-two version if the functional mode uses byte serializer) is fed
to the CMU clock divider block. Depending on the configured functional
mode, the CMU clock divider block divides the high-speed serial clock to
generate the low-speed parallel clock that clocks the transceiver PCS logic
in the associated channel. The low-speed parallel clock is also forwarded
to the PLD logic array on the tx_clkoutor coreclkoutports.
The receiver PLL in each channel is also fed by an input reference clock.
The receiver PLL along with the clock recovery unit generates a
high-speed serial recovered clock and a low-speed parallel recovered
clock. The low-speed parallel recovered clock feeds the receiver PCS logic
until the rate matcher. The CMU low-speed parallel clock clocks the rest
of the logic from the rate matcher until the receiver phase compensation
FIFO. In modes that do not use a rate matcher, the receiver PCS logic is
clocked by the recovered clock until the receiver phase compensation
FIFO.
The input reference clock to the transmitter and receiver PLLs can be
derived from:
■
■
■
One of two available dedicated reference clock input pins (REFCLK0
or REFCLK1) of the associated transceiver block
PLD clock network (must be driven directly from an input clock pin
and cannot be driven by user logic or enhanced PLL)
Inter-transceiver block lines driven by reference clock input pins of
other transceiver blocks
Altera Corporation
May 2008
2–31
Arria GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
