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EP1AGX50DF780C6 参数 Datasheet PDF下载

EP1AGX50DF780C6图片预览
型号: EP1AGX50DF780C6
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 50160 CLBs, 640MHz, PBGA780, 29 X 29 MM, 1 MM PITCH, FBGA-780]
分类和应用: 现场可编程门阵列可编程逻辑LTE时钟
文件页数/大小: 296 页 / 3505 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Arria GX Architecture  
to the two ALUTs, one ALM can implement various combinations of two  
functions. This adaptability allows the ALM to be completely backward-  
compatible with four-input LUT architectures. One ALM can also  
implement any function of up to six inputs and certain seven-input  
functions.  
In addition to the adaptive LUT-based resources, each ALM contains two  
programmable registers, two dedicated full adders, a carry chain, a  
shared arithmetic chain, and a register chain. Through these dedicated  
resources, the ALM can efficiently implement various arithmetic  
functions and shift registers. Each ALM drives all types of interconnects:  
local, row, column, carry chain, shared arithmetic chain, register chain,  
and direct link interconnects. Figure 2–28 shows a high-level block  
diagram of the Arria GX ALM while Figure 2–29 shows a detailed view  
of all the connections in the ALM.  
Figure 2–28. High-Level Block Diagram of the Arria GX ALM  
carry_in  
shared_arith_in  
reg_chain_in  
To general or  
local routing  
dataf0  
datae0  
dataa  
datab  
datac  
To general or  
local routing  
adder0  
D
Q
reg0  
Combinational  
Logic  
datad  
datae1  
dataf1  
To general or  
local routing  
adder1  
D
Q
reg1  
To general or  
local routing  
carry_out  
shared_arith_out  
reg_chain_out  
Altera Corporation  
May 2008  
2–39  
Arria GX Device Handbook, Volume 1  
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