Adaptive Logic Modules
load acts as a preset when the asynchronous load data input is tied high.
When the asynchronous load/preset signal is used, the labclkena0
signal is no longer available.
The LAB row clocks [5..0]and LAB local interconnect generate the
LAB-wide control signals. The MultiTrack interconnects have inherently
low skew. This low skew allows the MultiTrack interconnects to
distribute clock and control signals in addition to data.
Figure 2–27 shows the LAB control signal generation circuit.
Figure 2–27. LAB-Wide Control Signals
There are two unique
clock signals per LAB.
6
Dedicated Row LAB Clocks
6
6
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
labclr1
labclk0
syncload
labclk1
labclk2
labclkena2
labclkena0
or asyncload
or labpreset
labclkena1
labclr0
synclr
The basic building block of logic in the Arria GX architecture is the ALM.
The ALM provides advanced features with efficient logic utilization. Each
ALM contains a variety of look-up table (LUT)-based resources that can
be divided between two adaptive LUTs (ALUTs). With up to eight inputs
Adaptive Logic
Modules
2–38
Altera Corporation
Arria GX Device Handbook, Volume 1
May 2008
ALTERA [ ALTERA CORPORATION ]
