Transceivers
Figure 2–20 show the Arria GX block in reverse serial pre-CDR loopback
mode.
Figure 2–20. Arria GX Block in Reverse Serial Pre-CDR Loopback Mode
Transmitter Digital Logic
Analog Receiver and
Transmitter Logic
BIST
PRBS
Generator
BIST
Incremental
Generator
TX Phase
Compensation
FIFO
Byte
Serializer
8B/10B
Encoder
Serializer
20
FPGA
Logic
Array
Reverse
Serial
Pre-CDR
Loopback
BIST
Incremental
Verify
BIST
PRBS
Verify
Byte
De-
serializer
Rate
Match
FIFO
Clock
De-
RX Phase
Compen-
sation
8B/10B
Decoder
Deskew
FIFO
Word
Aligner
Recovery
serializer
Unit
FIFO
Receiver Digital Logic
PCI Express (PIPE) Reverse Parallel Loopback
Figure 2–21 shows the data path for PCI Express (PIPE) reverse parallel
loopback. The reverse parallel loopback configuration is compliant with
the PCI Express (PIPE) specification and is available only on PCI Express
(PIPE) mode.
Figure 2–21. PCI Express (PIPE) Reverse Parallel Loopback
Transmitter PCS
Transmitter PMA
TX Phase
Compe-
nsation
FIFO
Byte
Serializer
8B/10B
Encoder
Serializer
PIPE
Interface
PIPE Reverse
Parallel Loopback
Receiver PCS
Receiver PMA
RX Phase
Clock
De-
Byte
De-
Serializer
Rate
Match
FIFO
Compe-
nsation
FIFO
8B/10B
Decoder
Word
Aligner
Recovery
Serializer
Unit
You can dynamically put the PCI Express (PIPE) mode transceiver in
reverse parallel loopback by controlling the tx_detectrxloopback
port instantiated in the MegaWizard Plug-In Manager. A high on the
2–28
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
ALTERA [ ALTERA CORPORATION ]
