Arria GX Architecture
Figure 2–19. Arria GX Block in Reverse Serial Loopback Mode
Transmitter Digital Logic
Analog Receiver and
Transmitter Logic
BIST
PRBS
Generator
BIST
Incremental
Generator
TX Phase
Compensation
FIFO
Byte
Serializer
8B/10B
Encoder
Serializer
20
FPGA
Logic
Array
Reverse
Serial
Loopback
BIST
BIST
PRBS
Verify
Incremental
Verify
Byte
De-
serializer
Rate
Match
FIFO
Clock
De-
RX Phase
Compen-
sation
8B/10B
Decoder
Deskew
FIFO
Word
Aligner
Recovery
serializer
Unit
FIFO
Receiver Digital Logic
Reverse Serial Pre-CDR Loopback
Reverse serial pre-CDR loopback mode uses the analog portion of the
transceiver. An external source (pattern generator or transceiver)
generates the source data. The high-speed serial source data arrives at the
high-speed differential receiver input buffer, loops back before the CRU
unit, and is transmitted though the high-speed differential transmitter
output buffer. It is for test or verification use only to verify the signal
being received after the gain and equalization improvements of the input
buffer. The signal at the output is not exactly what is received since the
signal goes through the output buffer and the VOD is changed to the VOD
setting level. Pre-emphasis settings have no effect.
Altera Corporation
May 2008
2–27
Arria GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
